In general, multi-chip package is an important task for entire semiconductor fabricating technique and there may be many kinds of packages in accordance with various chips. For example, the pads of chip should be ranged in array for flip chip packaging process. In case of conventional wire-bonding chip package, the bonding pads of chip should be ranged at periphery of an active surface. Therein, a chip suitable for wire-bonding to connect has bonding pads ranged in single-side, two-side such as in “L” shape or “I I” shape, or four-side disposition. However, while proceeding multi-chip packaging process, the chip having bonding pads in asymmetric disposition will encounter difficulties in encapsulating processes.
Referring to FIG. 1, a well-known multi-chip package 100 comprises a substrate 110, a first chip 120, a second chip 130, a plurality of first bonding wires 141, a plurality of second bonding wires 142, a molding compound 150 and a plurality of external terminals 160. The first and second chips 120, 130 have bonding pads in asymmetric disposition respectively, there are a plurality of single-sided pads 122 disposed on one side of the active surface 121 of the first chip 120 and a plurality of single-sided pads 132 disposed on one side of the active surface 131 of the second chip 130.
The substrate 110 has an upper surface 111 and a lower surface 112, the first chip 120 is disposed on the upper surface 111 and the second chip 130 is stacked on the first chip 120 in a manner that the second chip 130 will not to cover the single-side pads 122 of the first chip 120. The first bonding wires 141 are applied for electrically connecting the single-side pads 122 of the first chip 120 to the substrate 110 and the second bonding wires 142 are also applied for electrically connecting the single-side pads 132 of the second chip 130 to the substrate 110. The molding compound 150 is formed over the upper surface 111 of the substrate 110 to encapsulate the first chip 120, the second chip 130, the first bonding wires 141 and the second bonding wires 142. The external terminals 160 such as solder balls are disposed on the lower surface 112 of the substrate 110. In the foregoing conventional multi-chip package 100, the substrate 110 spends much toward the entire packaging cost and the area of that the first chip 120 is directly encapsulated by the molding compound 150 is small, so that it is subject to inner stress to result in delamination problem. Additionally, the higher the chips are superimposed in dislocation, the longer the bonding wires connecting the chip need.
A multi-chip package wire-bonding on single-side bonding pads of a chip has been disclosed in U.S. Pat. No. 6,498,391 (as same as R.O.C. Taiwan Patent No. 404,030), which typically utilizes a leadframe with asymmetric leads (one side has longer leads and another side has shorter leads in length) to carry two chips with single-side pads. The longer leads at one side of leadframe are interposed between two chips superimposed in dislocation and a molding compound formed with transfer molding method encapsulates the two chips and inner ends of the two-side asymmetric leads. According to characteristic and direction of mold-flow, a gap located in where the long side leads are interposed between two chips is unable to be filled completely, thus the bubbles existing in the gap will cause serious delamination and popcorn problems to lower product reliability.